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TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM MT4LC4M4E8, MT4C4M4E8 MT4LC4M4E9, MT4C4M4E9
DRAM
FEATURES
* Industry-standard x4 pinout, timing, functions and packages * State-of-the-art, high-performance, low-power CMOS silicon-gate process * Single power supply (+3.3V 0.3V or +5V 10%) * All inputs, outputs and clocks are TTL-compatible * Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR) * Optional Self Refresh (S) for low-power data retention * 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh) * Extended Data-Out (EDO) PAGE MODE access cycle * 5V-tolerant inputs and I/Os on 3.3V devices
PIN ASSIGNMENT (Top View) 24/26-Pin SOJ (DA-2)
VCC DQ1 DQ2 WE# RAS# *NC/A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14
VSS DQ4 DQ3 CAS# OE# A9 A8 A7 A6 A5 A4 VSS
24/26-Pin TSOP (DB-2)
VCC DQ1 DQ2 WE# RAS# *NC/A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 VSS DQ4 DQ3 CAS# OE# A9 A8 A7 A6 A5 A4 VSS
OPTIONS
* Voltages 3.3V 5V * Refresh Addressing 2,048 (i.e. 2K) Rows 4,096 (i.e. 4K) Rows * Packages Plastic SOJ (300 mil) Plastic TSOP (300 mil) * Timing 50ns access 60ns access * Refresh Rates Standard Refresh Self Refresh (128ms period)
MARKING
LC C E8 E9 DJ TG -5 -6 None S
* NC on 2K refresh and A11 on 4K refresh options. Note: The "#" symbol indicates signal is active LOW.
4 MEG x 4 EDO DRAM PART NUMBERS
PART NUMBER MT4LC4M4E8DJ MT4LC4M4E8DJS MT4LC4M4E8TG MT4LC4M4E8TGS MT4LC4M4E9DJ MT4LC4M4E9DJS MT4LC4M4E9TG MT4LC4M4E9TGS MT4C4M4E8DJ MT4C4M4E8DJS MT4C4M4E8TG MT4C4M4E8TGS MT4C4M4E9DJ MT4C4M4E9DJS MT4C4M4E9TG MT4C4M4E9TGS Vcc 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 5V 5V 5V 5V 5V 5V 5V 5V REFRESH 2K 2K 2K 2K 4K 4K 4K 4K 2K 2K 2K 2K 4K 4K 4K 4K PACKAGE SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP REFRESH Standard Self Standard Self Standard Self Standard Self Standard Self Standard Self Standard Self Standard Self
* Part Number Example: MT4LC4M4E8DJ-6
Note: The 4 Meg x 4 EDO DRAM base number differentiates the offerings in two places - MT4LC4M4E8. The third field distinguishes the low voltage offering: LC designates VCC = 3.3V and C designates VCC = 5V. The fifth field distinguishes various options: E8 designates a 2K refresh and E9 designates a 4K refresh for EDO DRAMs.
KEY TIMING PARAMETERS
SPEED -5 -6
tRC tRAC tPC tAA t CAC tCAS
GENERAL DESCRIPTION
The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address
84ns 104ns
50ns 60ns
20ns 25ns
25ns 30ns
13ns 15ns
8ns 10ns
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TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM
GENERAL DESCRIPTION (continued)
(the latter 11 bits for 2K and the latter 10 bits for 4K, address pins A10 and A11 are "don't care"). READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates READ mode, while a logic LOW on WE# dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFYWRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE# LOW, no write will occur, and the data outputs will drive read data from the accessed location. The four data inputs and the four data outputs are routed through four pins using common I/O, and pin direction is controlled by WE# and OE#. with a row address strobed-in by RAS#, followed by a column address strobed-in by CAS#. CAS# may be toggled-in by holding RAS# LOW and strobing-in different column addresses, thus executing faster memory cycles. Returning RAS# HIGH terminates the PAGE MODE of operation, i.e., closes the page.
EDO PAGE MODE
The 4 Meg x 4 EDO DRAM provides EDO PAGE MODE, which is an accelerated FAST PAGE MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS# returns HIGH. EDO allows CAS# precharge time (tCP) to occur without the output data going invalid. This elimination of CAS# output control allows pipeline READs. FAST PAGE MODE DRAMs have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO PAGE MODE DRAMs operate like FAST PAGE MODE DRAMs, except data will remain valid or become valid after CAS# goes HIGH during READs, provided RAS# and OE# are held LOW. If OE# is pulsed while RAS# and CAS# are LOW, data will toggle from valid data to High-Z and back to the same valid data. If OE# is toggled or pulsed after CAS# goes HIGH while RAS# remains LOW, data will transition to and remain High-Z (refer to
PAGE ACCESS
PAGE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a row addressdefined page boundary. The PAGE cycle is always initiated
RAS# V IH V IL
CAS#
ADDR
DQ V IOH V IOL
,, ,,, ,,,,, ,,,,,C ,,,,, ,,,, ,, , ,, , ,
V IH V IL V IH V IL ROW COLUMN (A) COLUMN (B) OLUMN (C) COLUMN (D) OPEN V IH V IL
OE#
,,
VALID DATA (A) t OD
VALID DATA (A)
t OES
t OE
,,, ,,
VALID DATA (B) t OD t OEHC
VALID DATA (C)
t OD
,
VALID DATA (D)
t OEP
The DQs go back to Low-Z if tOES is met.
The DQs remain High-Z until the next CAS# cycle if tOEHC is met.
The DQs remain High-Z until the next CAS# cycle if tOEP is met.
, , ,,
,,
DON'T CARE UNDEFINED
Figure 1 OE# CONTROL OF DQs
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
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4 MEG x 4 EDO DRAM
fresh cycle and holding RAS# LOW for the specified tRASS. Additionally, the "S" option allows for an extended refresh period of 128ms, or 31.25s per row for a 4K refresh and 62.5s per row for a 2K refresh if using distributed CBR Refresh. This refresh rate can be applied during normal operation, as well as during a standby or BATTERY BACKUP mode. The Self Refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required upon exiting Self Refresh. However, if the DRAM controller utilizes a RAS#- ONLY or burst refresh sequence, all rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation.
Figure 1). WE# can also perform the function of disabling the output devices under certain conditions, as shown in Figure 2. During an application, if the DQ outputs are wire OR'd, OE# must be used to disable idle banks of DRAMs. Alternatively, pulsing WE# to the idle banks during CAS# high time will also High-Z the outputs. Independent of OE# control, the outputs will disable after tOFF, which is referenced from the rising edge of RAS# or CAS#, whichever occurs last.
REFRESH
Preserve correct memory cell data by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# refresh cycle (RAS#-ONLY, CBR or HIDDEN) so that all combinations of RAS# addresses (2,048 for 2K and 4,096 for 4K) are executed within tREF (MAX), regardless of sequence. The CBR and Self Refresh cycles will invoke the internal refresh counter for automatic RAS# addressing. An optional Self Refresh mode is also available on the S version. The "S" option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms. The optional Self Refresh feature is initiated by performing a CBR Re-
STANDBY
Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time.
RAS#
CAS#
ADDR
DQ V IOH V IOL
,, ,,, ,,,,,, ,,,,, ,,,,, ,,, , , ,, ,,
V IH V IL V IH V IL V IH V IL ROW COLUMN (A) COLUMN (B) COLUMN (C) COLUMN (D) OPEN V IH V IL V IH V IL
WE#
,,
VALID DATA (A)
t WHZ
t WPZ
,
VALID DATA (B)
INPUT DATA (C)
t WHZ
,,
OE#
The DQs go to High-Z if WE# falls and, if tWPZ is met, will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated).
WE# may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated).
Figure 2 WE# CONTROL OF DQs
,, ,, , ,,
DON'T CARE UNDEFINED
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
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4 MEG x 4 EDO DRAM
FUNCTIONAL BLOCK DIAGRAM - 2K REFRESH
WE# CAS#
DATA-IN BUFFER
4
NO. 2 CLOCK GENERATOR
DATA-OUT BUFFER
4 4
DQ1 DQ2 DQ3 DQ4
OE# COLUMN ADDRESS BUFFER(11) REFRESH CONTROLLER
COMPLEMENT SELECT
11 11 ROW ADDRESS BUFFERS (11)
ROW SELECT (2 of 4096)
11
ROW DECODER
2048 2048 2048 2048
2048
4096 x 1024 x 4 MEMORY ARRAY
RAS#
NO. 1 CLOCK GENERATOR
ROW TRANSFER ROW TRANSFER (1 OF 2) (1 OF 2)
VDD VSS
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
11
10 1
COLUMN DECODER
1024
4
SENSE AMPLIFIERS I/O GATING
1024 REFRESH COUNTER
FUNCTIONAL BLOCK DIAGRAM - 4K REFRESH
WE# CAS#
DATA-IN BUFFER
4
NO. 2 CLOCK GENERATOR
DATA-OUT BUFFER
4 4
DQ1 DQ2 DQ3 DQ4
OE# COLUMN ADDRESS BUFFER(10) REFRESH CONTROLLER
COMPLEMENT SELECT
12
ROW SELECT (1 of 4096)
ROW DECODER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
10
10
COLUMN DECODER
1024
4
SENSE AMPLIFIERS I/O GATING
1024 REFRESH COUNTER 4096 x 1024 x 4 MEMORY ARRAY
12
ROW ADDRESS BUFFERS (12)
4096 4096
12
4096
RAS#
NO. 1 CLOCK GENERATOR
VDD VSS
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4 MEG x 4 EDO DRAM
TRUTH TABLE
ADDRESSES FUNCTION Standby READ EARLY WRITE READ WRITE EDO-PAGE-MODE READ EDO-PAGE-MODE EARLY WRITE EDO-PAGE-MODE READ-WRITE HIDDEN REFRESH RAS#-ONLY REFRESH CBR REFRESH SELF REFRESH 1st Cycle 2nd Cycle 1st Cycle 2nd Cycle Any Cycle 1st Cycle 2nd Cycle READ WRITE RAS# H L L L L L L L L L L LHL LHL L HL HL CAS# HX L L L HL HL HL HL LH HL HL L L H L L WE# X H L HL H H L L H HL HL H L X H H OE# X L X LH L L X X L LH LH L X X X X
tR tC
DATA-IN/OUT DQ1-DQ4 High-Z Data-Out Data-In Data-Out, Data-In Data-Out Data-Out Data-In Data-In Data-Out Data-Out, Data-In Data-Out, Data-In Data-Out Data-In High-Z High-Z High-Z
X ROW ROW ROW ROW n/a ROW n/a n/a ROW n/a ROW ROW ROW X X
X COL COL COL COL COL COL COL n/a COL COL COL COL n/a X X
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4 MEG x 4 EDO DRAM
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to VSS: 3.3V ................................................................ -1V to +4.6V 5V ...................................................................... -1V to +7V Voltage on NC, Inputs or I/O Pins Relative to VSS: 3.3V ................................................................ -1V to +5.5V 5V ...................................................................... -1V to +7V Operating Temperature, TA (ambient) .......... 0C to +70C Storage Temperature (plastic) .................... -55C to +150C Power Dissipation ............................................................. 1W Short Circuit Output Current ..................................... 50mA
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1) 3.3V PARAMETER/CONDITION Supply Voltage Input High Voltage: Valid Logic 1; all inputs, I/Os and any NC Input Low Voltage: Valid Logic 0; all inputs, I/Os and any NC Input Leakage Current: Any input at VIN (0V VIN VIH [MAX]); all other pins not under test = 0V Output High Voltage: IOUT = -2mA (3.3V), -5mA (5V) Output Low Voltage: IOUT = 2mA (3.3V), 4.2mA (5V) Output Leakage Current: Any output at VOUT (0V VOUT 5.5V); DQ is disabled and in High-Z state SYMBOL VCC VIH VIL II MIN 3.0 2.0 -1.0 -2 MAX 3.6 5.5 0.8 2 MIN 4.5 2.4 -0.5 -2 5V MAX 5.5 VCC +1 0.8 2 UNITS V V V A 4 NOTES
VOH VOL IOZ
2.4 -5
0.4 5
2.4 -5
0.4 5
V V A
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4 MEG x 4 EDO DRAM
Icc OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3) 3.3V PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS# = VIH) STANDBY CURRENT: CMOS (non-S version only) (RAS# = CAS# = other inputs = VCC -0.2V) STANDBY CURRENT: CMOS (S version only) (RAS# = CAS# = other inputs = VCC -0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: EDO PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) REFRESH CURRENT: Extended (S version only) Average power supply current: CAS# = 0.2V or CBR cycling; RAS# = tRAS (MIN); WE# = VCC -0.2V; A0-A11,OE# and DIN = VCC -0.2V or 0.2V (DIN may be left open) REFRESH CURRENT: Self (S version only) Average power supply current: CBR with RAS# tRASS (MIN) and CAS# held LOW; WE# = VCC -0.2V; A0-A11, OE# and DIN = VCC -0.2V or 0.2V (DIN may be left open) SYM ICC1 ICC2 ICC2 5V NOTES
2K 4K 2K 4K SPEED Refresh Refresh Refresh Refresh UNITS ALL ALL ALL -5 -6 -5 -6 -5 -6 -5 -6 1 500 150 110 100 110 100 110 100 110 100 1 500 150 90 80 100 90 90 80 90 80 1 500 150 140 130 110 100 140 130 140 130 1 500 150 120 110 100 90 120 110 120 110 mA A A mA
5, 6
ICC3
mA
5, 6
ICC4
mA
5, 6
ICC5
mA
5, 7
ICC6
ALL ICC7
tRC
300 62.5
300 31.25
300 62.5
300 31.25
A s
5, 7 25
ICC8
ALL
300
300
300
300
A
5, 7
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4 MEG x 4 EDO DRAM
CAPACITANCE
PARAMETER Input Capacitance: Address pins Input Capacitance: RAS#, CAS#, WE#, OE# Input/Output Capacitance: DQ SYMBOL CI1 CI2 CIO MAX 5 7 7 UNITS pF pF pF NOTES 8 8 8
AC ELECTRICAL CHARACTERISTICS
(Notes: 2, 3, 9, 10, 11, 12, 17) (VCC [MIN] VCC VCC [MAX])
AC CHARACTERISTICS PARAMETER Access time from column address Column address setup to CAS# precharge Column address hold time (referenced to RAS#) Column address setup time Row address setup time Column address to WE# delay time Access time from CAS# Column address hold time CAS# pulse width CAS# LOW to "don't care" during Self Refresh CAS# hold time (CBR Refresh) CAS# to output in Low-Z Data output hold after next CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time Write command to CAS# lead time Data-in hold time Data-in setup time Output disable Output Enable OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay -5 SYMBOL tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCHD tCHR tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH
tOEHC tOEP tOES tOFF
-6 MAX 25 MIN 15 45 0 0 49 13 15 10 10 15 10 0 3 10 5 45 5 35 10 10 0 0 10 10 5 5 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
MIN 12 38 0 0 42 8 8 15 8 0 3 8 5 38 5 28 8 8 0 0 8 5 5 4 0
13 14
10,000
7
15
28
35
13 16 16 17 18 18
12 12
15 15
12
15
20
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4 MEG x 4 EDO DRAM
AC ELECTRICAL CHARACTERISTICS
(Notes: 2, 3, 9, 10, 11, 12, 17) (VCC [MIN] VCC VCC [MAX])
AC CHARACTERISTICS PARAMETER OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column address delay time Row address hold time RAS# pulse width RAS# pulse width (EDO PAGE MODE) RAS# pulse width during Self Refresh Random READ or WRITE cycle time RAS# to CAS# delay time Read command hold time (referenced to CAS#) Read command setup time Refresh period (2,048 cycles) Refresh period (4,096 cycles) Refresh period S version RAS# precharge time RAS# to CAS# precharge time RAS# precharge time exiting Self Refresh Read command hold time (referenced to RAS#) RAS# hold time READ WRITE cycle time RAS# to WE# delay time Write command to RAS# lead time Transition time (rise or fall) Write command hold time Write command hold time (referenced to RAS#) WE# command setup time Output disable delay from WE# Write command pulse width WE# pulse to disable at CAS# HIGH WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tORD
tPC tPRWC tRAC tRAD tRAH tRAS tRASP tRASS tRC tRCD tRCH tRCS tREF tREF tREF tRP tRPC tRPS tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP
-6 MAX MIN 0 25 56 50 60 12 10 60 60 100 104 14 0 0 MAX UNITS ns ns ns ns ns ns ns ns s ns ns ns ns ms ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
MIN 0 20 47 9 9 50 50 100 84 11 0 0
19 21
10,000 125,000
10,000 125,000
22 23
32 64 128 30 5 90 0 13 116 67 13 2 8 38 0 0 5 10 8 8 40 5 105 0 15 140 79 15 2 10 45 0 0 5 10 10 10
32 64 128
23
13
50
50
13
12
15
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4 MEG x 4 EDO DRAM
NOTES
1. All voltages referenced to VSS. 2. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C TA 70C) is ensured. 3. An initial pause of 100s is required after power-up, followed by eight RAS# refresh cycles (RAS#-ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 4. NC pins are assumed to be left floating and are not tested for leakage. 5. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 6. Column address changed once each cycle. 7. Enables on-chip refresh and address counters. 8. This parameter is sampled. VCC = VCCMIN; f = 1 MHz. 9. AC characteristics assume tT = 2.5ns. 10. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 11. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 12. Measured with a load equivalent to two TTL gates and 100pF; and VOL = 0.8V and VOH = 2V. 13. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. tRWD, tAWD and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tWCS < tWCS (MIN) and tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-MODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. OE# held HIGH and WE# taken LOW after CAS# goes LOW results in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 14. Requires that tAA and tRAC are not violated. 15. If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS# must be pulsed HIGH for tCP. 16. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 17. If OE# is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not permissible and should not be attempted. Additionally, WE# must be pulsed during CAS# HIGH time in order to place I/O buffers in High-Z. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS# remains LOW and OE# is taken back LOW after tOEH is met. If CAS# goes HIGH prior to OE# going back LOW, the DQs will remain open. 19. Requires that tAA and tCAC are not violated. 20. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. It is referenced from the rising edge of RAS# or CAS#, whichever occurs last. 21. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC and tCAC must always be met. 22. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. 23. Either tRCH or tRRH must be satisfied for a READ cycle. 24. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 25. The refresh period is extended from 32ms (2K refresh) or 64ms (4K refresh) to 128ms (both 2K and 4K refreshes). For 4K refresh, tRC = 31.25s (128ms/ 4,096 rows = 31.25s) and for 2K refresh, tRC = 62.5s (128ms/2,048 rows = 62.5s).
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.
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4 MEG x 4 EDO DRAM
READ CYCLE
tRC tRAS tRP
RAS#
V IH V IL tCSH tRSH tCRP tRCD tCAS tRRH
CAS#
ADDR
WE#
DQ
OE#
, ,,,, ,,,,, , ,,, , , , ,, , ,, , ,, ,,,,,,,,,,,,,,,,,, , ,, ,, , ,
V IH V IL tAR tRAD tRAH tASR tASC tCAH tACH V IH V IL ROW COLUMN ROW tRCS tRCH V IH V IL tAA tRAC tCAC tCLZ NOTE 1 tOFF V OH V OL OPEN VALID DATA OPEN t OE t OD V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tAA tACH tAR tASC tASR tCAC tCAH tCAS tCLZ tCRP tCSH tOD tOE
-6 MAX 25 MIN 15 45 0 0 13 15 10 10,000 10 0 5 45 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOFF tRAC tRAD tRAH tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH
-5 MIN 0 9 9 50 84 11 0 0 30 0 13 MAX 12 50 MIN 0 12 10 60 104 14 0 0 40 0 15
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 0 0 8 8 0 5 38 0
10,000
10,000
12 12
15 15
NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
11
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM
EARLY WRITE CYCLE
tRC tRAS tRP
RAS#
V IH V IL tCSH tRSH tCAS
, ,,, ,,,,, ,, , ,, , ,,,,, ,,,, ,,,, ,,, , ,,,, , , , ,,,, , ,, , ,, , , ,, , , , ,, ,, ,,
tCRP tRCD CAS# V IH V IL tAR tRAD tRAH tASC tCAH tASR tACH ADDR V IH V IL ROW COLUMN ROW tCWL tRWL tWCR tWCH tWP tWCS WE# V IH V IL tDS tDH V DQ V IOH IOL V IH V IL VALID DATA OE#
TIMING PARAMETERS
-5 SYMBOL tACH
tAR tASC tASR tCAH tCAS tCRP tCSH tCWL tDH tDS tRAD
,,
-6 MIN 10 60 104 14 40 15 15 10 45 0 5
DON'T CARE UNDEFINED
-6 MAX MIN 15 45 0 0 10,000 10 10 5 45 10 10 0 12 10,000 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tRAH
tRAS tRC tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP
-5 MIN 9 50 84 11 30 13 13 8 38 0 5 MAX 10,000
MIN 12 38 0 0 8 8 5 38 8 8 0 9
MAX 10,000
UNITS ns ns ns ns ns ns ns ns ns ns ns
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
12
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM
READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC tRAS tRP
RAS#
V IH V IL tCSH tRSH tCAS
ADDR
TIMING PARAMETERS
,, ,,, ,,,, ,, ,, , , , , , ,, , ,,, , ,, , ,, , , ,, ,,,,,,,,,, ,,,, ,, , , ,, , ,
tCRP tRCD CAS# V IH V IL tAR tRAD tASC tCAH tASR tRAH tACH V IH V IL ROW COLUMN ROW tRWD tCWL tRWL tWP tRCS tCWD tAWD WE# V IH V IL tAA tRAC tCAC t CLZ tDS tDH V DQ V IOH IOL OPEN VALID D OUT tOD VALID D IN OPEN tOE tOEH OE# V IH V IL
DON'T CARE UNDEFINED
-5 SYMBOL
tAA tACH tAR tASC tAWD tASR tCAC tCAH tCAS tCLZ tCRP tCSH tCWD tCWL tDH tDS
-6 MAX 25 MIN 15 45 0 49 0 13 15 10 10 0 5 45 35 10 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOD tOE tOEH tRAC tRAD tRAH tRAS tRCD tRCS tRP tRSH tRWC tRWD tRWL tWP
-5 MIN 0 8 50 9 9 50 11 0 30 13 116 67 13 5 10,000 12 10 60 14 0 40 15 140 79 15 5 MAX 12 12 MIN 0 10
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 0 42 0 8 8 0 5 38 28 8 8 0
10,000
10,000
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
13
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM
EDO-PAGE-MODE READ CYCLE
tRASP tRP
RAS#
V IH V IL tCSH tCRP tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP
CAS#
ADDR
WE#
DQ
OE#
,, ,,, ,,, ,,, ,, ,, ,, ,, ,, ,,,,,,,, , , ,,
V IH V IL tAR tRAD tRAH tASR tACH tASC tACH tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN tRCS V IH V IL tAA tAA tRAC tCAC tCPA tCAC tCLZ tCOH V OH V OL OPEN VALID DATA VALID DATA tOE tOD V IH V IL tOES
tACH tASC
COLUMN
tCLZ
tOEHC
tOEP
,,,, ,, , ,, , ,,,, , ,, , ,
tCAH ROW tRCH tAA tRRH tCPA tCAC tOFF VALID DATA OPEN tOE tOD tOES
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA tACH
tAR tASC tASR tCAC tCAH tCAS tCLZ tCOH tCP tCPA tCRP tCSH tOD tOE
-6 MAX 25 MIN 15 45 0 0 13 15 10 10,000 10 0 3 10 28 35 5 45 12 12 0 15 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOEHC tOEP
tOES tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH
-5 MIN 5 5 4 0 20 50 9 9 50 11 0 0 30 0 13 125,000 12 10 60 14 0 0 40 0 15 MAX MIN 10 5 5 0 25
-6 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 0 0 8 8 0 3 8 5 38 0
12
15 60
125,000
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
14
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM
EDO-PAGE-MODE EARLY WRITE CYCLE
tRASP tRP
RAS#
V IH V IL tCSH tPC tCP tRSH tCAS tCRP tRCD tCAS tCAS tCP tCP
CAS#
ADDR
WE#
V DQ V IOH IOL V IH V IL
OE#
,, , , , , , ,,,,, , , , , , ,,,, ,,, ,, ,,,,, ,,, , , ,, , , ,, , ,, ,,,,,,,,,,,,,,,,, , ,, ,
V IH V IL tAR tRAD tACH tACH tACH tASR tRAH tASC tCAH tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN COLUMN ROW tCWL tWP tCWL tWP tCWL tWP tWCS tWCH tWCS tWCH tWCS tWCH V IH V IL tWCR tDH tDS tDS tDH tDS tRWL tDH VALID DATA VALID DATA VALID DATA
TIMING PARAMETERS
-5 SYMBOL tACH
tAR tASC tASR tCAH tCAS tCP tCRP tCSH tCWL tDH tDS
,
-6 MAX
DON'T CARE UNDEFINED
-6 MAX MIN 15 45 0 0 10 10 10 5 45 10 10 0 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tPC
tRAD tRAH tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP
-5 MIN 20 9 9 50 11 30 13 13 8 38 0 5 125,000 MAX MIN 25 12 10 60 14 40 15 15 10 45 0 5
MIN 12 38 0 0 8 8 8 5 38 8 8 0
UNITS ns ns ns
125,000
10,000
10,000
ns ns ns ns ns ns ns ns ns
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
15
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP tRP
RAS#
V IH V IL tCSH t PC tPRWC NOTE 1 tRSH tCAS tCRP tRCD tCAS tCP tCAS tCP tCP
CAS#
ADDR
TIMING PARAMETERS
,, ,,,,,,,, , , ,, , , ,, , ,,,, ,, , ,, ,, , , ,,,,,,, ,, , , ,, ,, , , ,,, ,
V IH V IL tAR tRAD tRAH tASR tASC tCAH tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN COLUMN ROW tRWD tRCS tRWL tCWL tCWL tWP tAWD tCWD tWP tAWD tCWD tAWD tCWL tWP tCWD WE# V IH V IL tAA tAA tAA tRAC tDH tDS tCPA tDH tDS tCPA tDH tDS tCAC tCLZ tCAC tCLZ tCAC tCLZ DQ V IOH V IOL OPEN
VALID D OUT VALID D IN VALID D OUT VALID D IN VALID D OUT VALID D IN
OPEN
tOD
tOD
tOD
tOE
tOE
tOE
tOEH
OE#
V IH V IL
DON'T CARE UNDEFINED
-5 SYMBOL tAA tAR
tASC tASR tAWD tCAC tCAH tCAS tCLZ tCP tCPA tCRP tCSH tCWD tCWL tDH tDS
-6 MAX 25 MIN 45 0 0 49 13 15 10 10,000 10 0 10 28 35 5 45 35 10 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOD tOE
tOEH tPC tPRWC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWD tRWL tWP
-5 MIN 0 8 20 47 50 9 9 50 11 0 30 13 67 13 5 125,000 12 10 60 14 0 40 15 79 15 5 MAX 12 12 MIN 0 10 25 56
-6 MAX 15 15 UNITS ns ns ns ns 60 ns ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 42 8 8 0 8 5 38 28 8 8 0
125,000
NOTE: 1. tPC is for LATE WRITE cycles only.
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
16
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM
EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
t RASP t RP
RAS#
V IH V IL t CSH t PC t CRP t RCD t CAS t CP t CAS t PC t CP t CAS t RSH t CP
CAS#
ADDR
WE#
DQ V IOH V IOL
OE#
,,,,, ,,, ,,,, ,,, , ,, ,, ,,,,,,, ,, ,, ,
V IH V IL t AR t RAD t ACH t CAH tASR t RAH t ASC t CAH t ASC t CAH t ASC V IH V IL ROW COLUMN (A) COLUMN (B) COLUMN (N) t RCS t RCH t WCS t WCH V IH V IL t AA t AA t RAC t CPA t CAC t CAC t DS t DH t COH t WHZ OPEN VALID DATA (A) VALID DATA (B) VALID DATA IN t OE V IH V IL
ROW
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA tACH
tAR tASC tASR tCAC tCAH tCAS tCOH tCP tCPA tCRP tCSH tDH tDS
-6 MAX 25 MIN 15 45 0 0 13 15 10 10,000 10 3 10 28 35 5 45 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOE tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRSH tWCH tWCS tWHZ
-5 MIN 20 50 9 9 50 11 0 0 30 13 8 0 0 125,000 12 10 60 14 0 0 40 15 10 0 0 MAX 12 25 MIN
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 0 0 8 8 3 8 5 38 8 0
125,000
12
15
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
17
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM
READ CYCLE (With WE#-controlled disable)
RAS#
V IH V IL tCSH
CAS#
ADDR
WE#
DQ
OE#
, ,,, ,,,,, ,, ,, , ,, , , ,, ,, ,,,,,,, , ,, , , , ,, ,, ,, , ,
tCRP tRCD tCAS tCP V IH V IL tAR tRAD tRAH tASR tASC tCAH tASC V IH V IL ROW COLUMN COLUMN tRCS tRCH tWPZ tRCS V IH V IL tAA tRAC tCAC tCLZ tWHZ tCLZ V OH V OL OPEN VALID DATA t OD OPEN t OE V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA tAR tASC
tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH
-6 MAX 25 MIN 45 0 0 13 15 10 10 0 10 5 45 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOD tOE tRAC
tRAD tRAH tRCD tRCH tRCS tWHZ tWPZ
-5 MIN 0 MAX 12 12 50 MIN 0
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns 15 ns ns
MIN 38 0 0 8 8 0 8 5 38
9 9 11 0 0 0 10 12
12 10 14 0 0 0 10
10,000
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
18
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM
RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON'T CARE)
tRC tRAS tRP
RAS#
CAS#
ADDR
V DQ V OH OL
,,
V IH V IL V IH V IL
V IH V IL
tCRP
tASR
tRAH
ROW
,,,,,, ,,, , ,
tRPC OPEN
ROW
CBR REFRESH CYCLE (Addresses and OE# = DON'T CARE)
tRP RAS# V IH V IL tRPC tRPC tRAS tRP tRAS
CAS#
DQ
WE#
,,,,,,,,,,,,,,,,, ,, ,, ,, ,
tCP tCSR tCHR tCSR tCHR V IH V IL V OH V OL OPEN tWRP tWRH tWRP tWRH V IH V IL
,
MIN 60 104 40 5 10 10
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tASR
tCHR tCP tCRP tCSR tRAH
-6 MAX MIN 0 10 10 5 5 10 MAX UNITS ns ns ns ns ns ns SYMBOL tRAS
tRC tRP tRPC tWRH tWRP
-5 MIN 50 84 30 5 8 8 MAX 10,000
-6 MAX 10,000 UNITS ns ns ns ns ns ns
MIN 0 8 8 5 5 9
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
19
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM
HIDDEN REFRESH CYCLE 24 (WE# = HIGH; OE# = LOW)
tRAS tRP tRAS
RAS#
CAS#
ADDR
, ,,,,,,,,,,,,, , ,, , , , , , ,, ,,,,,,,, , ,,, , ,,, ,, ,
tCRP tRCD tRSH tCHR V IH V IL tAR tRAD tASR tRAH tASC tCAH V IH V IL ROW COLUMN tAA tRAC tCAC tCLZ tOFF V DQ V OH OL OPEN VALID DATA OPEN tOE tOD V OE# V IH IL tORD
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tAA tAR tASC tASR tCAC tCAH tCHR tCLZ tCRP tOD
-6 MAX 25 MIN 45 0 0 13 15 10 10 0 5 12 0 15 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL
tOE tOFF tORD tRAC tRAD tRAH tRAS tRCD tRP tRSH
-5 MIN 0 0 9 9 50 11 30 13 10,000 MAX 12 12 50 12 10 60 14 40 15 0 0 MIN
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 0 5 0
10,000
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
20
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM
SELF REFRESH CYCLE (Addresses and OE# = DON'T CARE)
NOTE 1 (( )) (( )) tRPS
RAS#
V IH V IL
CAS#
V IH V IL
DQ
V OH V OL
WE#
V IH V IL
,,,,, ,,,,, ,, , ,, ,, , ,, ,, ,, ,, , ,, , ,, , , , ,, ,
tRP tRASS NOTE 2 tRPC tCP tRPC (( )) tCSR tCHD tCP (( )) (( )) (( )) OPEN tWRP tWRH tWRP tWRH (( )) (( ))
TIMING PARAMETERS
-5 SYMBOL tCHD tCP tCSR tRASS tRP MIN 15 8 5 100 30 MAX MIN 15 10 5 100 40 -6 MAX UNITS ns ns ns s ns SYMBOL tRPC tRPS tWRH tWRP MIN 5 90 8 8 -5 MAX
,, ,,
-6 MIN 5 105 10 10
DON'T CARE UNDEFINED
MAX
UNITS ns ns ns ns
NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter Self Refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed.
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
21
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM
24/26-PIN PLASTIC SOJ (300 mil) DA-2
.679 (17.25) .673 (17.09)
.305 (7.75) .299 (7.59) .340 (8.64) .330 (8.38)
PIN #1 INDEX
.050 (1.27) TYP .600 (15.24) TYP
.037 (0.94) MAX DAMBAR PROTRUSION
.032 (0.81) .026 (0.66)
.142 (3.61) .132 (3.35) SEATING PLANE .020 (0.51) .015 (0.38) .109 (2.77) .094 (2.39) .040 (1.02) R .030 (0.76) .275 (6.99) .260 (6.60)
.025 (0.64) MIN
NOTE:
MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 1. All dimensions in inches (millimeters)
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
22
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM
24/26-PIN PLASTIC TSOP (300 mil) DB-2
.678 (17.23) .672 (17.07) .037 (0.95)
SEE DETAIL A
.367 (9.32) .359 (9.12) .302 (7.67) .298 (7.57)
PIN #1 INDEX .050 (1.27) TYP .020 (0.50) .012 (0.30)
.007 (0.18) .005 (0.13)
.004 (0.10) .047 (1.20) MAX .006 (0.15) .002 (0.05) DETAIL A
.010 (0.25)
GAGE PLANE
SEATING PLANE .024 (0.60) .016 (0.40) .032 (0.80) TYP
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900, Micron DataFax: 208-368-5800 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
4 Meg x 4 EDO DRAM D47.pm5 - Rev. 3/97
23
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1997, Micron Technology, Inc.

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